UART Logic Analyzer

Sequential digital

A transmitter frames a byte with a start bit, eight data bits LSB first, optional parity, and a stop bit. The receiver syncs on the start edge and samples at $(k+\tfrac12)T_{bit}(1+\varepsilon)$ by its own clock, so a clock error $\varepsilon$ accumulates across the frame and corrupts the last bits first.

Live circuit received 0x53 cleanly

UART Logic Analyzer

Drag the byte and the receiver-clock tags. The analyzer shows the line and every instant the receiver samples it.

Causal signal trace paused

Load the byte The transmitter adds a start bit, the data bits least significant first, optional parity, and a stop bit.

t_{\mathrm{stage}}=\htmlData{math-slot=value}{\mathtt{0.00}}\,\mathrm{s}

Step 1 / 5 Load the byte

Notebook: 8 parts and 7 wires, modelled as asynchronous framing + mid-bit sampling

Recommended lab 14 of 18

Explain asynchronous framing and the clock tolerance of mid-bit sampling.

Builds on: Maximal-Length LFSR

Predict, then test

The receiver’s clock runs $4\%$ fast. Which bits of the frame are most at risk?

Commit before the explanation appears. This is a prediction, not a quiz score.

Governing model

t_k = \left(k + \tfrac12\right) T_{bit}(1 + \varepsilon) \;\cdot\; |\varepsilon| \lesssim \dfrac{1}{2N_{bits}}

Parts

byte + TX shift register
single serial line
RX with independent baud clock
data + error outputs

Limits of the model

$8$ data bits, LSB first
parity none / even / odd
clock error $\pm10\%$

Diagnosis challenge The fault is hidden. Work it out from the changed outputs first.

Notebook: 8 parts and 7 wires, modelled as asynchronous framing + mid-bit sampling

The receiver’s clock runs 4%4\%4% fast. Which bits of the frame are most at risk?

The receiver’s clock runs $4\%$ fast. Which bits of the frame are most at risk?