Changelog

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No changes from 1.0.0. This version was tagged before the fixes meant for it were merged, so its package is 1.0.0's code under a new version number; those fixes shipped as 1.0.2. Upgrading from 1.0.0 to 1.0.1 changes nothing.

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1.0 is a rebuild of the compiler's core behind the same language and the same API. The language is read exactly as before — the 0.8 declaration patterns are the front end — and of the corpus's 54 rejections under 0.8, 52 are byte-identical in 1.0. Drawings change, because the router is new, and three corpus documents change outcome; each is listed under Changed. Wires are routed by net, and a mult

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### Added - **`trunk` draws a multi-terminal net as a tree.** A net reaching four terminals used to be three wires that each ran back to the shared pin — stacked on one another where the router reused a channel, and meeting at T-junctions with no dot, which a reader cannot tell from a crossing. Mark a connection `[ortho trunk]` and it leaves the nearest copper its net already has instead of its o

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### Added - **A reversal bus routes at thirty-two wires, up from twelve.** When rip-up spends its whole budget the traces are no longer retried again in a different order — the bundle is laid out as a set. Every trace takes the same five-segment dogleg and they differ only in where each turns: rank decides an outbound column stepping inward from the source, an inbound column stepping inward from

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### Added - **`snapshotSchematic` — a text digest of a diagram's geometry**, at `@schemd/core/snapshot`. Every component rectangle and every trace vertex, rounded to the three decimals the SVG writer emits, in source order, behind a `schemd-snapshot 1` version line. Committed as a fixture, a routing change now shows up in a pull request as the handful of coordinates that moved rather than as a re

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### Added - **Relative placement.** A declaration can state where it sits instead of computing it: `resistor:R1 "1 kΩ" right-of VIN by 190 #amber`. Six relations — `right-of`, `left-of`, `above`, `below`, `aligned-x with`, `aligned-y with` — each taking a component or one of its terminals, and the four directions taking an optional `by` distance. `at (x, y)` is untouched, the two forms mix freely

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Every connection that declares a closed endpoint marker paints one. SVG resolves marker-start at the first vertex of a path element and marker-end at its last — not once per subpath — so the compound trace that default and embedded-css output emit showed a single arrowhead however many wires shared a batch. Three [arrow] connections in one colour produced three lines and one arrow. Connections car

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Geometry diagnostics say how to fix the diagram, not only what is wrong with it. An overlap now reports the amount and a coordinate that clears it — R2 overlaps R1 by 44 units horizontally; move R2 to x = 284, or use a UML container — expressed in the at (x, y) origin the author types rather than the derived body rectangle. The advice follows the axis the author already used to separate the pair,

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@schemd/core/netlist and @schemd/core/describe are importable. Both modules shipped in the tarball with no entry in the package exports map, so import '@schemd/core/netlist' failed with ERRPACKAGEPATHNOTEXPORTED while dist/netlist.js sat there unused — the netlist subpath since it was announced in 0.3.4, the describe subpath since 0.3.6. Nothing caught either, because every test imports from src,

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Diagrams can describe themselves. describeSchematic and describeNetlist derive a deterministic account of a document from its connectivity — scale and signal domain in one sentence fit for an alt attribute, an inventory grouped by kind, and one sentence per net naming the terminals it ties. Labels are flattened through the same mathLabelText the renderer uses, so V{in} is spoken as Vin and 1 k\Ome

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The router's spatial hash addresses both axes. Cells were keyed on x alone, so a single column held every obstacle stacked along it and a short segment paid the participation predicate and a slab test once per row — the quadratic term in routing a tall document. Obstacle and wire cells are now keyed on column and row, with a y-span rejection ahead of the exact predicates. Dense 16x16 routing drops

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Connectivity is now a first-class artifact. buildNetlist returns the nodes, nets, and edges behind a validated document, verifyNetlist runs deterministic design rules over that model, and inspectSchematic does both in one call. Seven rules ship: shorted supply rails, conflicting bus widths, mixed signal domains, unconnected components, duplicate connections, contended digital drivers, and disconne

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cnot is now an intrinsic two-track controlled-X with continuous control and target rails. Canonical in1/out1 and in2/out2 ports compose directly with quantum wires; legacy in, out, control, and target endpoint spellings remain valid. A Chromium golden locks the two-rail CNOT geometry and its reversed horizontal orientation.

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Signal connections now resolve to first-class net topology. Exact shared terminals and junction branches join implicitly, net=NAME joins disconnected segments explicitly, unnamed nets receive deterministic $N identities, and every net enforces one signal-domain/width contract. Straight, cubic Bézier, and orthogonal routes now share one collision policy across component bodies, transformed endpoint

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Orthogonal routing no longer fails diagrams whose components sit closer than twice the 12-unit clearance margin. The post-routing guard now rejects only physical body clips; escape stubs may legitimately pass through a neighbor's clearance ring, so densely packed parallel wires route as straight traces instead of throwing Orthogonal route intersects … after routing. Empty qgate detail rows (parame

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Exact quarter-turn component orientation through orientation=right|down|left|up, including rotated ports, outward normals, AABBs, text extents, obstacle routing, and four-turn identity. Electrical sources, native junctions/test points/connectors, power symbols, switch and protection families, amplifiers, resonators, meters, loads, expanded passive/diode/transistor variants, and side-aware IC orien

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Last 0.2.x release. Historical documentation remains at the official 0.2.1 route.

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