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Closed-Loop Buck Converter

Power electronics

A synchronous step-down converter with a continuous-time $L$ – $C$ state solver and switching-ripple reconstruction. Sweep duty cycle, source voltage, load, inductance, capacitance, and carrier frequency; the laboratory identifies conduction mode, efficiency, ripple, and transient settling in real time.

12 components · 15 connections · continuous-time averaged state space

the aha
Chop a voltage fast enough, and an inductor plus a capacitor remember only its average.

why it works

A resistor divider would burn the excess voltage as heat. A buck converter refuses to waste it: the switch turns the input fully on and fully off at high frequency, and the

L

–

C

pair acts as a flywheel that averages the chopping. Sit in continuous conduction and the average obeys the beautifully simple

v_o = D\,V_{in}

— the output is just the input scaled by the fraction of time the switch is closed. The governing pair

\dot i_L = \frac{DV_{in}-v_o}{L},\ \dot v_o = \frac{i_L - v_o/R}{C}

shows the inductor current and output voltage chasing each other toward that average, with efficiency the divider could never touch.

governing model

\dot i_L = \dfrac{D V_{in}-v_o}{L},\quad \dot v_o = \dfrac{i_L-v_o/R}{C}

structural inventory

PWM feedback controller
PMOS high-side switch
Schottky freewheel diode
$L$ – $C$ output network

boundaries

$V_{in}: 5$ – $36\ \mathrm V$
$f_{sw}: 20$ – $500\ \mathrm{kHz}$
CCM / BCM / DCM classification

fault relay high-side MOSFET gate drive lost

Sweep the duty cycle $D$ .

The regulated rail tracks $D\,V_{in}$ almost exactly — you are setting an output voltage by setting a fraction of time, not by dissipating the difference.
Drop the load current until conduction goes discontinuous.

Watch the classifier flip CCM → BCM → DCM as the inductor current hits zero each cycle. The simple $D\,V_{in}$ law quietly stops holding.
Kill the high-side gate drive.

With the switch stuck open, the flywheel coasts to zero — the averaging engine has lost its energy source.

causal signal trace paused

Sample demand The controller compares feedback against the regulation target.

t_{stage} = 0.00 s

step 1 / 5 Sample demand

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