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8-Bit Digital Adder

Digital

Eight full-adder cells built from XOR/AND/OR primitives. Clicking an input port toggles a bit and dispatches one synchronous logic pass; high nets glow as the carry ripples left to right.

66 components · 89 connections · event-driven Boolean solver

the aha
Addition is fast, but the carry is a rumour — and a rumour has to travel.

why it works

Each bit of the answer needs two facts: the sum

S_i = A_i \oplus B_i \oplus C_i

and the carry it hands upward,

C_{i+1} = A_iB_i + C_i(A_i \oplus B_i)

. The

\oplus

(XOR) tells you the bit; the AND/OR pair tells you whether a

1

spilled over. Here is the catch a newcomer never sees on paper: bit $i$ cannot finish until bit $i-1$ has decided its carry. So the truth does not appear everywhere at once — it ripples, one cell at a time, from the least significant bit to the most. That travel time is exactly why real processors abandon this circuit for carry-lookahead.

governing model

S_i = A_i \oplus B_i \oplus C_i \;\cdot\; C_{i+1} = A_iB_i + C_i(A_i \oplus B_i)

structural inventory

$8\times$ full-adder cell
$16\times$ XOR + $16\times$ AND
$8\times$ OR carry merge
$A/B/C_{in}$ + Sum ports

boundaries

$8$ -bit operands · $0$ – $255$
sum $0$ – $511$ with carry-out
per-gate propagation delay

fault relay carry chain stuck-at-0

Type two numbers and watch the front move.

Set $A$ and $B$ , then watch the glow: the low bits settle first and a bright carry front climbs upward. You are literally watching information propagate.
Toggle bit 0 of an all-ones operand.

Flip the lowest bit of $A = 11111111$ and a single carry sweeps all the way to $C_{out}$ — one bit of input, eight cells of consequence. This is the worst case, $t \propto n$ .
Throw the stuck-at-0 fault.

Freeze the carry chain and the sum silently loses its overflow. The bits still light up — the rumour just never arrives.

causal signal trace paused

Sample A, B, and $C_{in}$ The input register changes now; no sum output is allowed to jump ahead of the carry front.

t_{stage} = 0.00 s

step 1 / 10 Sample A, B, and Cᵢₙ

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