8-Bit Digital Adder

Digital

Eight full-adder cells built from XOR/AND/OR primitives. Changing an operand or carry input dispatches one synchronous logic pass; high nets glow as the carry ripples left to right.

live circuit · mode=full 43 + 86 = 129

8-Bit Digital Adder

direct manipulation enabled Click any A, B, or C_in port in the schematic

Click an input port to flip its bit; the carry ripples through the chain.

causal signal trace paused

Sample A, B, and $C_{\mathrm{in}}$ The input register changes now; no sum output is allowed to jump ahead of the carry front.

t_{\mathrm{stage}}=\htmlData{math-slot=value}{\mathtt{0.00}}\,\mathrm{s}

step 1 / 10 Sample A, B, and Cᵢₙ

Notebook · 66 parts · 89 wires · event-driven Boolean solver

recommended lab 1 of 18

Trace a carry dependency through a combinational gate network.

Prerequisite: none — start here.

predict · then test

Before running $11111111_2 + 1_2$ : which part of the result can settle first?

Commit before the explanation appears. This is a prediction, not a quiz score.

governing model

S_i = A_i \oplus B_i \oplus C_i \;\cdot\; C_{i+1} = A_iB_i + C_i(A_i \oplus B_i)

structural inventory

$8\times$ full-adder cell
$16\times$ XOR + $16\times$ AND
$8\times$ OR carry merge
$A/B/C_{in}$ + Sum ports

boundaries

$8$ -bit operands · $0$ – $255$
sum $0$ – $511$ with carry-out
per-gate propagation delay

diagnosis challenge Fault identity withheld: infer it from the changed outputs first.

Notebook · 66 parts · 89 wires · event-driven Boolean solver

Before running 111111112+1211111111_2 + 1_2111111112​+12​: which part of the result can settle first?

Before running $11111111_2 + 1_2$ : which part of the result can settle first?