Phase-Locked Loop

Active analog

A sinusoidal phase detector compares the reference with the VCO, a first-order $RC$ loop filter smooths the error into $v_c$ , and the VCO retunes to $\omega_0+K_vv_c$ . The state $(\theta_e, v_c)$ is integrated live, so acquisition, lock, and cycle slipping all appear on the scope and in the phase portrait.

live circuit · mode=full locked · phase offset 0°

Phase-Locked Loop

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causal signal trace paused

Compare the phases The detector multiplies the reference by the fed-back VCO output; its average is proportional to the sine of the phase error.

t_{\mathrm{stage}}=\htmlData{math-slot=value}{\mathtt{0.00}}\,\mathrm{s}

step 1 / 5 Compare the phases

Notebook · 9 parts · 10 wires · nonlinear phase-error dynamics

recommended lab 15 of 18

Explain lock as a steady phase error and find the hold range of a PLL.

Builds on: Wien-Bridge Oscillator

predict · then test

The loop is locked to a reference $500\ \mathrm{Hz}$ above the VCO’s free-running frequency. What is the steady phase error $\theta_e$ ?

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governing model

\dot\theta_e = \omega_{ref} - (\omega_0 + K_v v_c) \;\cdot\; \tau\,\dot v_c = K_d \sin\theta_e - v_c

structural inventory

reference oscillator $f_{ref}$
XOR phase detector $K_d\sin\theta_e$
$RC$ loop filter
VCO $\omega_0+K_vv_c$

boundaries

$f_{ref},\ f_0: 8$ – $12\ \mathrm{kHz}$
hold range $\pm K_vK_d=\pm1.2\ \mathrm{kHz}$
$\tau=RC: 0.05$ – $2\ \mathrm{ms}$

diagnosis challenge Fault identity withheld: infer it from the changed outputs first.

Notebook · 9 parts · 10 wires · nonlinear phase-error dynamics

The loop is locked to a reference 500 Hz500\ \mathrm{Hz}500 Hz above the VCO’s free-running frequency. What is the steady phase error θe\theta_eθe​?

The loop is locked to a reference $500\ \mathrm{Hz}$ above the VCO’s free-running frequency. What is the steady phase error $\theta_e$ ?