Maximal-Length LFSR
Sequential digitalA 4-bit Fibonacci linear-feedback shift register with taps at stages 3 and 4 — the primitive polynomial . Each clock edge shifts the register and feeds back the XOR of the tapped bits. The result cycles through all 15 non-zero states before repeating: a deterministic sequence wearing the disguise of randomness.
7 components · 11 connections · clocked shift register over GF(2)
Connect primitive feedback taps to the period of an LFSR sequence.
Builds on: 8-Bit Digital Adder
Move one feedback tap away from the primitive polynomial. Must the period remain ?
Commit before the explanation appears. This is a prediction, not a quiz score.
- shared clock
- D flip-flop chain
- XOR feedback taps
- serial m-sequence output
- period
- all-zero state forbidden
- primitive polynomial taps
Form the feedback bit Before the edge, the selected Q3 and Q4 taps XOR to establish the next D input.
step 1 / 4 Form the feedback bit
control console
test bed · mode=full
instrumentation rack
register
- 0
- 0
- 0
- 1
register value
8sequence period
15output bit
Primitive taps — all 15 non-zero states before repeating.