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Adaptive Clock-Recovery PLL

Control + RF

A phase/frequency detector, charge pump, passive loop filter, VCO, and programmable divider form a complete frequency-synthesis loop. Change the reference, divide ratio, bandwidth, and damping; the phase-domain solver reveals pull-in, overshoot, control-voltage motion, lock confidence, and cycle slips.

11 components · 12 connections · second-order phase-domain loop

the aha

A loop that does nothing but chase its own phase error will tune an oscillator until it agrees with a clock it has never been told the frequency of.

why it works
The VCO free-runs at some frequency; the divider slices it by NN; the phase detector compares that against a reference and coughs up an error. Feed the error back through a filter to the VCO’s tuning voltage, and the loop hunts until the error is zero — at which point fout=Nfreff_{out} = N f_{ref}, locked. The dynamics are those of a mass on a spring: e¨+2ζωne˙+ωn2e=0\ddot e + 2\zeta\omega_n\dot e + \omega_n^2 e = 0, where the damping ζ\zeta decides whether lock is a graceful glide or a ringing overshoot. The aha is that a purely reactive circuit — one that only ever reacts to being wrong — synthesises an exact integer multiple of a frequency nobody programmed in.
governing model
fout=Nfref,e¨+2ζωne˙+ωn2e=0f_{out}=Nf_{ref},\quad \ddot e + 2\zeta\omega_n\dot e + \omega_n^2e=0
structural inventory
  • phase/frequency detector
  • charge pump + loop filter
  • voltage-controlled oscillator
  • programmable ÷N\div N feedback
boundaries
  • N:2N: 2–6464
  • loop bandwidth 0.20.2–8 kHz8\ \mathrm{kHz}
  • lock threshold ±50 ppm\pm 50\ \mathrm{ppm}
fault relay reference clock disconnected

  1. Watch the control voltage acquire lock.

    From a cold start, VctrlV_{ctrl} ramps and settles as the phase error drives to zero. When it flatlines, fout=Nfreff_{out} = N f_{ref} to within the lock threshold.

  2. Lower the damping ζ.

    Underdamp the loop and lock arrives with overshoot and ringing — the same second-order behaviour as a springy suspension. Too little damping and it barely settles.

  3. Disconnect the reference.

    With nothing to compare against, the loop loses its truth and the VCO drifts back to its free-running frequency. The synthesiser was only ever borrowing accuracy from the reference.
causal signal trace paused

Compare phases The PFD compares reference and divided feedback edges.

step 1 / 5 Compare phases

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