Use the strict 0.3 grammar

01 / NodesDeclare one bounded component per line

The declaration grammar is kind:ID "label" at (x, y) #color [options]. Identifiers are stable source-map keys. Unknown, duplicated, or kind-incompatible options fail with a one-based line diagnostic.

orientation accepts only right, down, left, or up. It is rejected for rotationally meaningless nodes such as junction. Logical port names never rotate.

resistor:R0 "right" at (130, 150) #amber [orientation=right]
resistor:R1 "down" at (330, 150) #cyan [orientation=down]
resistor:R2 "left" at (530, 150) #purple [orientation=left]
resistor:R3 "up" at (730, 150) #emerald [orientation=up]

02 / WiresConnect semantic ports and signal domains

Connections use A.port -> B.port #color [options]. Routes are line, bezier, or ortho. Signal domains are electrical, digital, quantum, and classical; width mismatches are rejected before layout.

port:INPUT "D[7:0]" at (80, 140) #blue [width=8]
register:REG "R0" at (330, 140) #cyan [width=8]
port:OUTPUT "Q[7:0]" at (650, 140) #emerald [width=8]
INPUT.out -> REG.in #blue [digital width=8]
REG.out -> OUTPUT.in #emerald [digital width=8]

Connection options also include net, marker-start, marker-end, label, UML relations, and dashed. Full mode emits source-line metadata for nodes, ports, and wires.

net=NAME gives signal segments one explicit topology identity. Names begin with an ASCII letter, contain only letters, digits, _, or -, and are at most 64 characters. Segments sharing an exact component.port join implicitly, so every branch declared through the same junction.node inherits one net, and a name may also join geometrically disconnected segments. Every segment in one net must use the same signal domain and width; conflicting names at a shared terminal are errors. UML relations cannot declare nets. Unnamed signal topologies receive deterministic source-ordered $1, $2, … identities in the AST, source map, and full-mode SVG (data-net-id).

Geometry is contract-checked at compile time. Physical component bodies may touch at an edge but cannot overlap (UML containers and lifeline overlays may intentionally contain children). All route families are collision checked: straight and cubic paths cannot penetrate unrelated bodies or earlier connector labels, orthogonal paths route around bodies and labels while pricing earlier unrelated wire channels as soft occupancy, and transformed endpoint-marker footprints participate in the same rule. Separate nets may cross only as a strict perpendicular orthogonal crossing — which receives a bridge on the later trace — while same-net contacts stay continuous with no bridge. Collinear overlap between separate nets, endpoint contact, diagonal or cubic crossings, and bridge clusters too dense to render are compile errors with source-line diagnostics.

03 / ValidationUse family options, never untyped attributes

Common family options are type, orientation, inputs, outputs, width, controls, targets, wires, parameter, phase, matrix, operator, and control. Availability is defined per kind in the component API.

source:AC "AC" at (100, 150) #blue [type=voltage-ac orientation=down]
buffer:BUF "3-state" at (340, 150) #cyan [type=tristate orientation=left]
controlled:CU "U" at (580, 150) #purple [controls=2 targets=1 operator="R_z"]
component:CPU "controller" at (790, 150) #slate [width=150 height=90]