node kind:ID "label" at (x, y) #color [options]
wire A.port -> B.port #color [line|bezier|ortho]
tree A.port -> C.port #color [ortho trunk]
block subcircuit NAME [p="v"] { … expose T = X.port }
place NAME:ID at (x, y) [p="v"]
passive resistor capacitor inductor
analog diode transistor port ground
electrical source junction testpoint connector power switch protection amplifier resonator meter load
logic nand nor xor xnor and or not
digital buffer logic clock flipflop mux encoder decoder register counter adder comparator bus
quantum hadamard cnot qgate xgate ygate zgate sgate sdg tgate tdg sx phase rx ry rz ugate
quantum systems measure reset prepare swap control cz cphase toffoli controlled barrier delay classical-bit classical-register
uml class interface provided-interface required-interface enumeration datatype object component component-port artifact node device execution system actor usecase state lifeline action decision merge fork join activity-final flow-final object-node send-signal receive-signal partition activation destruction fragment interaction gate found lost choice state-junction history entry exit terminate region note package initial final